A nibble-oriented CPU in Verilog to build a scientific calculator
Details
- External ID
- 48151237
- Source
- HN
- Company
- —
- Product
- A nibble-oriented CPU in Verilog to build a scientific calculator
- Website domain
- github.com
- Launched
- May 15, 2026
- Cohort
- —
- Upvotes
- 119
- Upvotes percentile
- 0.9240710823909531
- Tags
- —
- Fetched at
- Sept. 7, 2026, 9:26 p.m.
- Updated at
- Sept. 7, 2026, 9:26 p.m.
Description
The core question: how did HP's scientific calculators actually work at the gate level? That rabbit hole led to building one from scratch.The architectural decision everything else follows from: a decimal calculator should store numbers as BCD — one decimal digit per 4-bit nibble. A standard byte-oriented CPU (Z80, 6502) fights that layout constantly. So I designed a small custom CPU in Verilog where 4 bits is the natural data width and memory is nibble addressable.What the project covers:- Custom CPU: Harvard architecture, 12-bit ISA, 8-state execution FSM, hardware stack guard with a FAULT state for microcode debugging- CORDIC for trig functions, verified to 14 significant digits- Two-pass assembler in Python (~700 lines)- Verilator + Qt framework: same Verilog source runs in simulation, as a desktop GUI debugger, as WebAssembly, and on real hardware- Scripting language on top of the microcode for adding functions without touching hardware- Custom PCB (EasyEDA/JLCPCB), battery, charging circuitWrite-up: https://baltazarstudios.comHackaday: https://hackaday.com/2026/05/13/build-the-cpu-then-build-the...
Enrichment
- Theme
- lightweight and on-device AI runtimes
- Vertical
- Horizontal
- Function
- Hardware & robotics
- Audience
- Developer
- AI stance
- Not AI
- Project type
- Hobby / open-source project
- Normalized one-liner
- cpu in verilog for scientific calculator
- Manually corrected
- False
Could you build this?
No Designing a custom processor in Verilog requires specialized digital logic, computer microarchitecture design, and hardware description expertise that AI assistants cannot reliably produce or synthesize.
What it would actually take: Building a nibble-oriented BCD processor requires designing register-transfer level (RTL) Verilog for a 4-bit ALU capable of BCD arithmetic (including 10's complement and correction logic), a microprogrammed or hardwired control unit, a program counter, and memory interfaces. The calculator firmware requires implementing CORDIC or polynomial approximation algorithms in microcode or assembly for transcendental functions, verified through cycle-accurate digital simulation (e.g., Verilator) and targeted to an FPGA. This demands deep digital engineering expertise in timing closure, finite state machines, and hardware debugging.
Discussion
20 comments analyzed.
Competitors mentioned: HP calculators (35, 45, 55, 65, 67, 20-series, 30-series, 11C, 15C), MicroPython calculator, 6502 processor (BCD mode comparison), Z80 processor
Concerns raised: 4-bit architecture doesn't align with standard byte-addressable CPU design, Ghidra disassembler lacks support for non-byte-aligned memory regions, Video documentation quality limitations, HP calculator power adapter design flaw - high voltage damage without battery pack
Feature requests: Ghidra support for 4-bit architectures, Better quality video tutorials/documentation
Competitors
Other products that read as similar to this one — 40 launches clear the similarity bar, closest 8 shown.
Attention rank: #3 of 41 (itself plus its competitors, highest first — normalized so YC and Product Hunt are compared fairly).
Launched 191 days after the earliest competitor.
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Other launches for this product
- No other launches for this product.
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