RISCY-V02: A 16-bit 2-cycle RISC-V-ish CPU in the 6502 footprint
Details
- External ID
- 47269683
- Source
- HN
- Company
- —
- Product
- RISCY-V02: A 16-bit 2-cycle RISC-V-ish CPU in the 6502 footprint
- Website domain
- github.com
- Launched
- March 6, 2026
- Cohort
- —
- Upvotes
- 7
- Upvotes percentile
- 0.4108241082410824
- Tags
- —
- Fetched at
- Sept. 7, 2026, 9:26 p.m.
- Updated at
- Sept. 7, 2026, 9:26 p.m.
Description
Finally finished my little CPU project, RISCY-V02. I built it (with Claude) to challenge the notion that the 6502 was a "local optimum" in its transistor budget. Given the constraints of 1970s home computers (~1 MHz DRAM, so raw clock speed doesn't help), could RISC have been a better design choice? This design argues yes: pipelining, barrel shifters, and more registers beat microcode PLAs, questionable addressing modes, and hardware BCD.Highlights:8x 16-bit general-purpose registers (vs 3x 8-bit on 6502)2-stage pipeline (Fetch/Execute) with speculative fetch61 fixed 16-bit instructions2-cycle interrupt entry (vs 7 on 6502)13,844 SRAM-adjusted transistors (vs 13,176 for 6502 on same process)1.0-2.6x faster than 6502 across common routinesGDS viewer: https://mysterymath.github.io/riscyv02-skyTiny Tapeout Shuttle Entry: https://app.tinytapeout.com/projects/3829
Enrichment
- Theme
- lightweight and on-device AI runtimes
- Vertical
- —
- Function
- Hardware & robotics
- Audience
- Developer
- AI stance
- Not AI
- Project type
- Hobby / open-source project
- Normalized one-liner
- risc-v cpu in 6502 footprint
- Manually corrected
- False
Could you build this?
No Designing a custom CPU architecture to fit physical transistor budgets and clock cycle constraints of vintage hardware requires deep digital logic and computer architecture expertise.
What it would actually take: Building this requires HDL (Verilog/VHDL or SystemVerilog), cycle-accurate simulators like Verilator, and synthesis/timing analysis tools targeting an FPGA or ASIC pinout compatible with the 6502 socket. The hard part is microarchitecture design: implementing a 2-cycle instruction pipeline and decoder within an ultra-constrained transistor budget and memory bus protocol. This requires specialized computer engineering knowledge in computer architecture, gate-level optimization, and digital electronics.
Discussion
4 comments analyzed.
Competitors mentioned: 6502 CPU, 65C02 CPU, RISC-V
Concerns raised: Uncertainty whether Tiny Tapeout will produce a functional chip, Transistor count comparison methodology unclear vs historical 6502, Cannot validate design works on actual 70s process
Competitors
Other products that read as similar to this one — 105 launches clear the similarity bar, closest 8 shown.
Attention rank: #67 of 106 (itself plus its competitors, highest first — normalized so YC and Product Hunt are compared fairly).
Launched 128 days after the earliest competitor.
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Other launches for this product
- No other launches for this product.