FPGA prime finder
discovered a 1,123-digit Proth prime
Details
- External ID
- 47095221
- Source
- HN
- Company
- —
- Product
- FPGA prime finder
- Website domain
- github.com
- Launched
- Feb. 20, 2026
- Cohort
- —
- Upvotes
- 5
- Upvotes percentile
- 0.10512129380053908
- Tags
- —
- Fetched at
- Sept. 7, 2026, 9:25 p.m.
- Updated at
- Sept. 7, 2026, 9:25 p.m.
Description
I built a Proth prime tester on a Zybo Z7-20 FPGA ($200 board) and found a new 1,123-digit prime: 2079 * 2^3718 + 1.Proth primes are numbers of the form k * 2^n + 1. They have a neat property: Proth's theorem gives you a deterministic proof of primality, not just a probabilistic test. If you can find an integer a where a^((p-1)/2) = -1 mod p, the number is proven prime. No "probably" about it.The interesting part is the hardware. The core is a 4096-bit Montgomery CIOS multiplier running on a Zynq-7020. It uses 28 DSP48E1 slices and runs at 74 MHz, doing one full modular multiply in ~8,514 clock cycles. The host PC runs an algebraic sieve (eliminates ~92% of candidates using discrete logarithms mod small primes), precomputes the Montgomery constants, then ships each candidate to the FPGA over UART at 115200 baud.PrimeGrid has exhaustively searched all k < 1200 up to n > 3,000,000. Everything above k = 1200 is wide open. I picked k = 2079 because my sieve showed it had the most surviving candidates at high n. Nobody had ever tested it before.The prime also divides 5 Generalized Fermat Numbers, which was an unexpected bonus.12 hardware bugs found along the way. Highlights: Vivado 2019.1 silently prunes register bits when a muxed datapath has sources of different widths. The Montgomery CIOS algorithm produces results in [0, 2p) not [0, p), and without normalizing after every multiply, the error compounds across thousands of squarings. Non-blocking assignments in Verilog mean your "combinational" readout is actually one cycle stale.All RTL (Verilog), Python scripts, and build files are open source.Verify it yourself: p = 2079 * (1 << 3718) + 1 print(pow(5, (p-1)//2, p) == p - 1) # Truehttps://github.com/0xdeadbeefnetwork/Optimus_Prime
Enrichment
- Theme
- scientific computing and deep tech tools
- Vertical
- Horizontal
- Function
- Hardware & robotics
- Audience
- Developer
- AI stance
- Not AI
- Project type
- Hobby / open-source project
- Normalized one-liner
- fpga accelerated prime number discovery
- Manually corrected
- False
Could you build this?
No Requires specialized hardware design expertise in Verilog/VHDL, FPGA architecture, and computational number theory to implement arbitrary-precision arithmetic pipelines on hardware.
What it would actually take: Building this requires writing HDL (Verilog/VHDL) targeting the Xilinx Zynq-7000 FPGA architecture on the Zybo Z7 board. The core challenge is implementing custom large-integer modular arithmetic, specifically Montgomery multiplication or FFT-based multiplication for thousand-digit numbers in hardware registers and DSP slices, constrained by clock timing and BRAM resources. It demands specialized digital logic design skills and mathematical expertise in implementing Proth primality testing algorithms.
Discussion
No comments on this launch.
Competitors
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Attention rank: #49 of 55 (itself plus its competitors, highest first — normalized so YC and Product Hunt are compared fairly).
Launched 87 days after the earliest competitor.
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- No other launches for this product.
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