Porting xv6 to HiFive Unmatched board
Details
- External ID
- 46565833
- Source
- HN
- Company
- —
- Product
- Porting xv6 to HiFive Unmatched board
- Website domain
- github.com
- Launched
- Jan. 10, 2026
- Cohort
- —
- Upvotes
- 26
- Upvotes percentile
- 0.6903820816864296
- Tags
- —
- Fetched at
- Sept. 7, 2026, 9:25 p.m.
- Updated at
- Sept. 7, 2026, 9:25 p.m.
Description
Hi HN,I ported the teaching OS xv6-riscv to HiFive Unmatched and got it running on real hardware, including passing usertests.I've been self-studying OS internals using the MIT 6.1810 materials. After finishing most of the labs, I was eager to see what it's like to run the OS on bare metal, rather than QEMU.The Unmatched may not have the latest RISC-V features, but it's well-documented, and the Rev B release has made it more affordable, which makes it a good learning platform.The porting process involved several interesting challenges:- Hardware Quirks: Handling things like enabling A/D bits in PTEs (the hardware doesn't set them automatically, causing page faults), proper handling of interrupts, and instruction cache synchronization.- Boot Flow: xv6 expects M-mode on startup, but standard RISC-V boot flows (typically via OpenSBI) jump to S-mode. To bridge this gap, I created a minimal U-Boot FIT image that contains only the xv6 kernel. This way, U-Boot SPL handles the complex CPU/DDR initialization, then hands control to xv6 in M-mode (skipping OpenSBI).- Drivers: Ported an SPI SD card driver, replacing the virtio disk driver.I wrote up implementation notes here: https://github.com/eyengin/xv6-riscv-unmatched/blob/unmatche...Hopefully, this is useful for others who are learning OS internals and want to try running their code on real RISC-V hardware.
Enrichment
- Theme
- systems tools and desktop utilities
- Vertical
- Horizontal
- Function
- Dev tools
- Audience
- Developer
- AI stance
- Not AI
- Project type
- Hobby / open-source project
- Normalized one-liner
- operating system porting for risc-v
- Manually corrected
- False
Could you build this?
No Porting an operating system kernel to bare-metal RISC-V hardware requires low-level assembly, device tree parsing, memory-mapped I/O, and hardware debugging expertise.
What it would actually take: Requires writing RISC-V assembly boot code, configuring the SiFive FU740/HiFive Unmatched MMU page tables, initializing system clocks/PLLs, and implementing device drivers for the physical UART, PLIC (interrupt controller), and PCIe/storage peripherals. Real hardware debugging demands hardware probes (JTAG), UART consoles, and deep knowledge of RISC-V privileged architecture specs. Vibe coding cannot autonomously debug low-level hardware register interactions or timing faults.
Discussion
4 comments analyzed.
Competitors mentioned: asciinema, svg-term-cli, VexRiscv
Competitors
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Attention rank: #28 of 79 (itself plus its competitors, highest first — normalized so YC and Product Hunt are compared fairly).
Launched 73 days after the earliest competitor.
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Other launches for this product
- No other launches for this product.
Same idea, different domain
Nobody's really built a dev tools tool for Sales yet.