ddr-resocket-multichannel-dma
Open-source multi-channel DDR DMA controller for FPGA: 4 write channels, 5 read channels, async FIFOs, address generation, and arbitration.
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GITHUB · launched Oct 23, 2026 · 55 upvotes (top 26%)
- Horizontal
- Hardware & robotics
- Developer
- Not AI
- Hobby / open-source project
- adc
- awg
- axi4
- clc
- cmp
- ddr
- +14 more
Similar launches
See all 162 similar launches →Could you build this?
No A multi-channel DDR DMA controller is FPGA/ASIC RTL design that needs hardware engineering, memory-interface timing expertise, and hardware verification.
What it would actually take: The core is synthesizable HDL (Verilog/SystemVerilog) with async clock-domain-crossing FIFOs, arbitration, and address generation, tuned to a specific DDR PHY and memory controller. Building it properly requires hardware design experience, simulation and verification infrastructure, and FPGA toolchain and timing-closure work on real boards.
Competitors
Other products that read as similar to this one : 162 launches clear the similarity bar, closest 8 shown.
Attention rank: #34 of 163 (itself plus its competitors, highest first, normalized so YC and Product Hunt are compared fairly).
Launched 345 days after the earliest competitor.
- 100t-DMA-FPGA-Based-RISC-V-SoC · github · 2026-09-30 · 29 upvotes · similarity 0.58
- Reverse-engineered the FPGA bitstream using Claude Code · hn · 2026-04-06 · 6 upvotes · similarity 0.49
- Industrial DDR3 DRAM Chip · ph · 2026-09-16 · 1 upvotes · similarity 0.49
- 8Gb DDR4 DRAM Chip · Wide-temp · CN · ph · 2026-09-17 · 1 upvotes · similarity 0.47
- DMA-Attack-rpocket-Firmware-Customization · github · 2026-10-23 · 54 upvotes · similarity 0.46
- DMA-Attack-rpocket-Firmware-Customization · github · 2026-10-26 · 63 upvotes · similarity 0.46
- eft-dma-radar-rpocket · github · 2026-10-23 · 54 upvotes · similarity 0.46
- eft-dma-radar-rpocket · github · 2026-10-26 · 64 upvotes · similarity 0.46