100t-DMA-FPGA-Based-RISC-V-SoC
Full System-on-Chip implementation intended for synthesis on a Nexys A7 100T FPGA Board. Complete with UART Bootloader, DMA, Interrupts, and PWM
This is 1 of 595 launches in low-level systems and desktop utilities — see how it stacks up on momentum and crowding →
380 other launches read as similar to this one →
Details
- External ID
- 1398244143
- Source
- GITHUB
- Company
- —
- Product
- 100t-DMA-FPGA-Based-RISC-V-SoC
- Website domain
- github.com
- Launched
- Sept. 30, 2026
- Cohort
- —
- Upvotes
- 29
- Upvotes percentile
- 0.7140274765003616
- Tags
- —
- Fetched at
- Oct. 1, 2026, 1:02 a.m.
- Updated at
- Oct. 1, 2026, 1:02 a.m.
Enrichment
- Theme
- low-level systems and desktop utilities
- Vertical
- Manufacturing
- Function
- Hardware & robotics
- Audience
- Developer
- AI stance
- Not AI
- Project type
- Hobby / open-source project
- Normalized one-liner
- risc-v soc for nexys a7 fpga
- Manually corrected
- False
Could you build this?
No Designing and synthesizing an FPGA-based RISC-V SoC with custom DMA, UART bootloader, and interrupts requires deep electrical engineering and digital hardware description language (HDL) expertise.
What it would actually take: Built using Verilog/SystemVerilog targeting Xilinx Artix-7 (Nexys A7 100T) via Vivado tooling. It requires custom RTL for RISC-V core interfacing, memory controllers, DMA channels, interrupt handling, and bus protocols (like AXI or Wishbone), followed by strict timing closure, synthesis, and hardware-level oscilloscopes/logic analyzer debugging.
Competitors
Other products that read as similar to this one — 380 launches clear the similarity bar, closest 8 shown.
Attention rank: #108 of 381 (itself plus its competitors, highest first — normalized so YC and Product Hunt are compared fairly).
Launched 331 days after the earliest competitor.
- FPGA soft-core of the Saab Viggen's 1963 airborne computer · hn · 2026-03-20 · 22 upvotes · similarity 0.55
- amt-tools · github · 2026-09-14 · 15 upvotes · similarity 0.55
- Reverse-engineered the FPGA bitstream using Claude Code · hn · 2026-04-06 · 6 upvotes · similarity 0.54
- PocketOrca-LLM · github · 2026-09-14 · 8 upvotes · similarity 0.52
- chromatix · github · 2026-09-29 · 9 upvotes · similarity 0.51
- A tiny LLM running at 21,000 tok/s on a $250 FPGA (Live Demo) · hn · 2026-08-10 · 79 upvotes · similarity 0.50
- PALPack · github · 2026-09-20 · 16 upvotes · similarity 0.50
- ch341-to-mfi-chip · github · 2026-09-13 · 25 upvotes · similarity 0.50
Other launches for this product
- No other launches for this product.
Same idea, different domain
Nobody's really built a hardware & robotics tool for Horizontal yet.