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nocturne

arm64 hypervisor for exception routing + stage 2 isolation

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GITHUB · launched Oct 19, 2026 · 25 upvotes (top 56%)

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Could you build this?

No An arm64 hypervisor doing exception routing and stage-2 memory isolation is low-level systems work that requires deep knowledge of CPU architecture and virtualization.

What it would actually take: This needs ARM64 architecture expertise: EL2 setup, exception vector handling, stage-2 translation tables, and interrupt and timer virtualization, usually written in assembly and C. It requires hardware testing on real Apple or ARM silicon and careful debugging of faults that vibe coding cannot reliably produce. Security review is also essential.

Competitors

Other products that read as similar to this one : 2881 launches clear the similarity bar, closest 8 shown.

Attention rank: #1514 of 2882 (itself plus its competitors, highest first, normalized so YC and Product Hunt are compared fairly).

Launched 353 days after the earliest competitor.

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