The Thiele Machine
Coq-Verified Computational Model Beyond Turing
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The Thiele Machine is a formally verified universal computational model the surpasses Turing machines in key ways. It's fully proven in Coq (including kernel theorems and universality containment), features a python implementation for simulation and includes hardware designs in Verilog for potential FPGA/ASIC builds. The core idea: a paradigm shift using μ-bits for stricter computation under real-world constraints, tying into physics (e.g., Noether’s theorem) and emergence in chaotic systems.The repo includes a 13-chapter thesis (PDF and sources), proofs, and tools for exploration. It’s aimed at formal methods enthusiasts, AI researchers, and hardware devs interested in verifiable, adaptive reasoning beyond traditional limits. Feedback welcome on the proofs, emergence chapter, or hardware impl, let’s collaborate!
HN · launched Jan 12, 2026 · 9 upvotes (top 54%) · 0 views
Niche: specialized algorithms and computing libraries · 230 launches, 4 in the last 7 days ▼ -73% · Explore this niche →
Category and tags
- Horizontal
- Dev tools
- Developer
- Not AI
- Hobby / open-source project
Visit website ↗ Source listing ↗
More like this: all 230 launches in specialized algorithms and computing libraries →
Could you build this?
No Developing a novel computational model formally proven in Coq alongside Verilog hardware specifications is cutting-edge theoretical computer science and formal verification research.
What it would actually take: Requires deep expertise in theoretical computer science, interactive theorem proving (Coq), formal semantics, and digital logic design (Verilog). The hard parts are formulating non-trivial kernel theorems, maintaining soundness across universality containment proofs in Coq, and synthesizing functional Verilog descriptions.
Discussion
4 comments analyzed.
Concerns raised: Falsifiability of claims unclear despite Coq proofs, Skepticism about 'beyond Turing' framing and practical relevance, Simulation performance concerns
Feature requests: ASIC optimization for low-power emergent logic, Hardware acceleration beyond FPGA prototyping
Competitors
Other products that read as similar to this one : 416 launches clear the similarity bar, closest 8 shown.
Attention rank: #211 of 417 (itself plus its competitors, highest first, normalized so YC and Product Hunt are compared fairly).
Launched 73 days after the earliest competitor.
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- genpark-hoare-logic-axiomatic-verifier-skill · github · 2026-09-28 · 7 upvotes · similarity 0.46
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