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TinyGPU

Custom RVV 64 bit vector accelerator for the CVA6 RISC-V CPU. SIMD style layout with 3 memory hierarchies inside the accelerator.

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GITHUB · launched Sep 19, 2026 · 22 upvotes (top 36%) · 0 views

Niche: open-source hardware and maker electronics · 180 launches, 3 in the last 7 days ▼ -73% · Explore this niche →

Category and tags

  • Horizontal
  • Hardware & robotics
  • Developer
  • Not AI
  • Hobby / open-source project

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Could you build this?

No Designing a custom 64-bit RISC-V Vector (RVV) hardware accelerator with internal memory hierarchies for an existing CPU core is deep digital logic and semiconductor hardware engineering.

What it would actually take: Building this requires expert knowledge of hardware description languages (SystemVerilog or Chisel), computer architecture, and digital design verification. The architecture requires implementing an RVV-compliant SIMD execution pipeline integrated into the CVA6 core via an accelerator interface (such as CV-X-IF or RoCC), coupled with multi-level internal SRAM cache hierarchies, register files, and DMA controllers. Verification requires cycle-accurate hardware simulation (Verilator/Questa) and FPGA synthesis tooling.

Competitors

Other products that read as similar to this one : 1794 launches clear the similarity bar, closest 8 shown.

Attention rank: #676 of 1795 (itself plus its competitors, highest first, normalized so YC and Product Hunt are compared fairly).

Launched 325 days after the earliest competitor.

The niche, labels, vibe code rating and competitor comparison on this page are analysis by Nicheloom. If you use them, please credit nicheloom.com. How you may use our data.